A great reduction of the transistor feature size in recently developed deep-submicron CMOS processes shifts the design paradigm towards more digitally-intensive techniques. In a monolithic implementation, the manufacturing cost of a design is measured not in terms of a number of devices used but rather in terms of the occupied silicon area, and is little dependent on the actual circuit complexity. The testing part of the overall cost does indeed depend on the circuit complexity, but a large number of digital gates typically have a higher test coverage and lower testing cost than even a small analog circuit.
Each new digital CMOS process advance occurs roughly 18 months while increasing the digital gate density by a factor of two (known as the Moore's Law). A typical digital cellular phone on the market today contains over a million transistors. Analog and RF circuits, on the other hand, do not scale down very well. For example, a known CMOS process with 0.08 μm L-effective feature size achieves digital gate density of 150K equivalent (2-input NAND) gates per mm2, which is an order of magnitude greater than with more traditional RF BiCMOS process technologies. An average-size inductor for an integrated LC oscillator occupies about 0.5 mm2 of silicon area. A low-noise charge pump, or a low-distortion image-reject mixer, both good examples of classical RF transceiver components, occupy roughly about the same area, which could be traded for tens of thousands of digital gates, which is a lot of DSP power. Consequently, there are numerous incentives to look for digital solutions.
Migrating to the digitally-intensive RF front-end architecture could bring forth the following well-known advantages of a conventional digital design flow:                Fast design turn-around cycle using automated CAD tools (VHDL or Verilog hardware-level description language, synthesis, auto-place and auto-route with timing-driven algorithms, parasitic backannotation and postlayout optimization).        Much lower parameter variability than with analog circuits.        Ease of testability.        Lower silicon area and dissipated power that gets better with each CMOS technology advancement (also called a “process node”).        Excellent chances of first-time silicon success. Commercial analog circuits usually require several design, layout and fabrication iterations to meet marketing requirements.        
There is a wide array of opportunities that integration presents. The most straightforward way would be to merge various digital sections into a single silicon die, such as DRAM or flash memory embedded into DSP or controller. More difficult would be integrating the analog baseband with the digital baseband. Care must be taken here to avoid coupling of digital noise into the high-precision analog section, usually through substrate or power/ground supply lines. In addition, the low amount of voltage headroom challenges one to find new circuit and architecture solutions. Integrating the analog baseband into the RF transceiver section presents a different set of challenges: The conventional Bi-CMOS RF process is tuned for high-speed operation with a number of available passive components and does not fundamentally stress high precision.
Sensible integration of diverse sections results in a number of advantages:                Lower total silicon area. In a deep-submicron CMOS design, the silicon area is often bond-pad limited. Consequently, it is beneficial to merge various functions onto a single silicon die to maximize the core to bond-pad ratio.        Lower component count and thus lower packaging cost.        Power reduction. There is no need to drive large external inter-chip connections.        Lower printed-circuit board (PCB) area, thus saving the precious “real estate.”        
Deep-submicron CMOS processes present new integration opportunities on one hand, but make it extremely difficult to implement traditional analog circuits, on the other. For example, frequency tuning of a low-voltage deep-submicron CMOS oscillator is an extremely challenging task due to its highly nonlinear frequency vs. voltage characteristics and low voltage headroom making it susceptible to the power/ground supply and substrate noise. In such low supply voltage case, not only the dynamic range of the signal suffers but also the noise floor rises, thus causing even more severe degradation of the signal-to-noise ratio. At times, it is possible to find a specific solution, such as utilizing a voltage doubler. Unfortunately, with each CMOS feature size reduction, the supply voltage needs also to be scaled down, which is inevitable in order to avoid breakdown and reliability issues.
Moreover, the high degree of integration leads to generation of substantial digital switching noise that is coupled through power supply network and substrate into noise sensitive analog circuits. Furthermore, the advanced CMOS processes typically use low resistance P-substrate which is an effective means in combating latchup problems, but exacerbates substrate noise coupling into the analog circuits. This problem only gets worse with scaling down of the supply voltage. Fortunately, there is a serious effort today among major IC fabrication houses to develop CMOS processes with higher resistivity silicon substrates.
Circuits designed to ensure the proper operation of RF amplifiers, filters, mixers, and oscillators depend on circuit techniques that operate best with long-channel, thick-oxide devices with supply voltage of 2.5 V or higher. The process assumed herein for exemplary and explanatory purposes is optimized for short-channel, thin-oxide devices operating as digital switches at only 1.5 V.
In order to address the various deep-submicron RF integration issues, some new and radical system and architectural changes have to be discovered. Alternative approaches and architectures for RF front-end are herein explored. This will allow easy integration of RF section into digital baseband.
RF synthesizers, specifically, remain one of the most challenging tasks in mobile RF systems because they must meet very stringent requirements of a low-cost, low-power and low-voltage monolithic implementation while meeting the phase noise and switching transient specifications. They are being selected and ranked according to the following set of criteria:                Phase noise performance—as any analog circuits, oscillators are susceptible to noise, which causes adverse affects in the system performance during receive and transmit.        Discrete spurious noise performance—unwanted frequency components to appear in the oscillator output spectrum.        Switching speed—very important in modem communications systems which utilize channel and frequency hopping in order to combat various wireless channel impairments (fading, interference, etc.). Since the system switches carrier frequency often (as fast as once every 1.6 ms in BLUETOOTH), a fast switching and stable frequency synthesizer is essential for proper operation. Switching speed is also important in a fixed-channel time-division multiple access (TDMA) systems for quick handoff.        Frequency and tuning bandwidth—the frequency range has to cover the operational band and have enough margin for process-voltage-temperature variations.        Power consumption—important for battery operated mobile communication units.        Size—important for mass production deployment.        Integrateability—utilizing the deep-submicron CMOS process technology in order to integrate with digital baseband.        Cost—no extra cost added to the process. Requires minimal amount of external components (so called “bill of materials”).        Portability—ability to transfer the design from one application to another and from one process technology node to the next. An important issue in digital VLSI and for intellectual property (IP)-based applications. Designs described in a hardware description language (HDL) are very portable.        
The present invention provides an all-digital frequency synthesizer architecture built around a digitally controlled oscillator that is tuned in response to a digital tuning word. In exemplary embodiments: (1) a gain characteristic of the digitally controlled oscillator can be determined by observing a digital control word before and after a known change in the oscillating frequency; (2) a portion of the tuning word can be dithered, and the resultant dithered portion can then be applied to a control input of switchable devices within the digitally controlled oscillator; and (3) a non-linear differential term can be used to expedite correction of the digitally controlled oscillator when large phase error changes occur.